An integrated circuit (IC) is a circuit whose components and connecting "wires" are formed by processing distinct areas of a chip of semiconductor material, such as silicon.
Sequential ICs are ICs that include a digital circuit whose operating "state" at an instant in time is determined at least in part by binary information that is stored in the digital circuit. Specifically, sequential ICs typically include both combinational circuitry (e.g., arrays of digital gates) and memory elements. Combinational circuitry generates binary output signals at any instant in time that are entirely dependent upon the input signals presented to the combinational circuitry at that instant. Memory elements store binary information so that it is available, for example, for use by the combinational circuitry. In operation, a sequential IC receives binary input signals from a host system. These binary input signals, together with the binary information stored by the memory elements, determine the binary output signals transmitted from the sequential IC to the host system. The binary input signals and stored binary information also determine the conditions required for changing the binary information stored in the memory elements. Therefore, a time sequence of input signals, output signals and internal memory states determines the operating "state" of the sequential IC.
"Synchronous" sequential ICs utilize clock signals such that all changes to the binary information stored in the memory elements takes place just after each clock signal pulse. A common memory element used in synchronous sequential ICs is referred to as a "flip-flop". A static flip-flop is a circuit that can maintain a binary state indefinitely (as long as power is applied to the IC) until directed by an input signal to switch states. The flip-flop switches states in response to, for example, a rising edge of a clock signal (i.e., when the clock signal changes from "0" (low) to "1" (high)). There are several types of known flip-flops, including D, RS, JK and T type flip-flops.
The development of an IC typically includes generating a circuit design, testing the circuit design to assure that it will perform as desired, and finally, laying out and fabricating a physical IC (or implementing the circuit in a programmable logic device). Circuit design testing typically involves forming a computer-based circuit description, and then using an IC simulation tool to simulate operation of the computer-based circuit description. As used below, "circuit design" refers generally to a circuit, whereas a "computer-based circuit description" is a software-based description of a circuit design that is stored in the memory of a computer. In contrast to a computer-based circuit description, the terms "integrated circuit" and "IC" refer to the physical implementation of the circuit design including, for example, a silicon semiconductor chip that is mounted in a ceramic or plastic package.
FIG. 1(A) shows a block diagram generally illustrating a system for testing circuit designs in accordance with known methods. The system includes a computer 100 such as an Ultra 1 workstation produced by Sun Microsystems, Inc. Computer 100 has a memory 101 for storing software tools including IC simulation software 102, such as the Verilog software program produced by Cadence Design, Inc. Memory 101 also stores a computer-based circuit description 104, which identifies all of the electronic components of a user's circuit design, including all interconnections (input nodes and output nodes) associated with the electronic components. In addition, a portion of memory 101 is reserved for test vector file 106 including signal values that are applied to test nodes of circuit description 104, and for test result file 108 that includes result data regarding the simulated operation of circuit description 104. A user 110 enters circuit description 104 and test vector file 106 into memory 101 using an input device 120, such as a keyboard and/or a mouse. Error messages and other data stored in test result file 108 are transmitted by computer 100, for example, to a display 130.
FIG. 1(B) is a graphical circuit description of a multiplexer (MUX) 140 that forms a part of circuit description 104. MUX 140 receives three input signals including a first data signal D0, a second data input signal D1 and a select input signal SEL. MUX 140 is a combinational electronic component in that when SEL is a logic "1" (e.g., high) signal, MUX 140 passes first data signal D0 to its output terminal, and when SEL is a logic "0" (e.g., low) signal, MUX 140 passes second data signal D0 to its output terminal.
FIGS. 1(C) and 1(D) provide graphical representations of a portion of a test vector file 106 and a test result file 108, respectively. These graphical representations, along with similar graphical representations referred to below, are provided merely to describe data organization and processing related to the conventional testing methods, and do not necessarily describe the actual data organization implemented in test vector file 106 and test result file 108.
Referring to FIG. 1(C), test vector file 106 includes a sequence of test vectors (numbered 0 through 7). Each test vector includes a set of signal values associated with first data signal D0, second data signal D1 and select signal SEL that are applied to the input nodes of MUX 140. Test vector file 106 is shown as being truncated to indicate that test vector values are also provided to other electronic components (not shown) of circuit description 104. In accordance with conventional test methods, circuit description 104 is tested by applying all possible input conditions using an iterative sequence, and by comparing the resulting output signals against expected values. Using a simple example, MUX 140 is tested by transmitting every possible combination of signals to the input terminals of MUX 140. That is, logic "1" and logic "0" values are transmitted to the input terminals of MUX 140 on first data signal D0, second data signal D1 and select signal SEL.
Referring to FIG. 1(D), the circuit responses (results) of circuit description 104 to the vectors applied by test vector file 106 are collected and compared in test result file 108. Test result file 106 is also shown as being truncated to indicate that test results are also provided from other electronic components (not shown) of circuit description 104. Each test vector result includes an expected output value (OE) and an actual output value (OA). The OE values are generated, for example, from a functional description of the circuit design. The OA values are generated, for example, from circuit description 104 that is entered into computer 100 using a graphical description tool. When circuit description 104 meets the requirements defined by the functional description, the OA values generated in response to the test vectors by the graphical representation coincide with the OE values (as shown in FIG. 1(D)). When the circuit description 104 does not meet the requirements defined by the functional description, the OA values differ from the OE values, and an error message is transmitted to display 130 notifying user 110. In response, user 130 typically alters circuit description 104 until errors are avoided.
Although the above-described conventional method of testing circuit designs works well for combinational circuit designs, problems may arise when it is used to test sequential circuit designs.
FIG. 1(E) is a graphical circuit description of a flip-flop (FF) 160 that forms a part of a sequential circuit description 104(2). FF 160 receives three input signals including a data signal D3, a clock signal CLK and a reset signal RST. FF 160 is a sequential electronic component in that the output signal OUT transmitted from output terminal Q changes in response to either data signal D3 or reset signal RST only during the rising edge of the CLK signal (i.e., when the clock signal changes from logic "0" to logic "1").
FIGS. 1(F) and 1(G) provide graphical representations of a portion of a test vector file 106(2) and a test result file 108(2), respectively. Referring to FIG. 1(F), according to the conventional test method, test vector file 106(2) includes the same iterative sequence of test vectors used above with respect to MUX 140, but the sets of signal values are associated with the clock signal CLK, data signal D3 and reset signal RST that are applied to the input nodes of FF 160. FIG. 1(G) shows test result file 108(2) that includes the circuit responses (results) of FF 160 to test vector file 106(2).
A first problem arising from using conventional iterative test vector sequences to test sequential circuit designs is that much of the generated data may be unusable. As mentioned above, the output signal generated by FF 160 changes only when clock signal CLK changes from "0" to "1", and does not test how the circuit design reacts to some signal transitions. Therefore, test vectors 0 through 3 (FIG. 1(F)) fail generate output signal changes even though data signal D3 and reset signal RST change from logic "0" to logic "1". For example, when reset signal RST changes from logic "0" to logic "1" (i.e., transition T1 between vectors 0 and 1), no change occurs in the output because clock signal CLK remains at logic "0" (indicated as C1). Similarly, when data signal D3 changes from logic "0" to logic "1" (i.e., transition T2 between vectors 0 and 1), no change occurs in the output because clock signal CLK remains low. Therefore, valuable time is spent generating test vectors that fail to provide usable results, thereby increasing the cost of IC development.
A second problem arising from using conventional iterative test vector sequences to test sequential circuit designs is that unexpected or erroneous test results may be generated. For example, referring to FIG. 1(F), when the clock signal CLK transitions from logic "0" to logic "1" (transitions T3 between vectors 3 and 4), an indeterminate. result may be generated if any other signals are also changing (such as data signal D3 and reset signal RST which change from logic "1" to logic "0"). These indeterminate results may generate incorrect error messages that may cause a user to spend needless amounts of time looking for errors in the circuit description.
A third problem arising from using conventional iterative test vector sequences to test sequential circuit designs is that the input nodes in some sequential circuits are subjected to floating ("tri-state") signal levels that are between logic "1" and logic "0". Because the conventional test method does not include floating signals in the iterative sequence of test vectors, the test results do not provide information regarding how the circuit design reacts to floating signals. Even more specifically, the test results do not provide information regarding how the circuit design reacts to transitions between logic "1" and "0" values and floating signals.
What is needed is a method for testing sequential circuit designs that overcomes the deficiencies described above with respect to conventional testing methods.